Axelera AI
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Senior R&D Engineer - RISC-V Memory Hierarchy (Italy/Europe based)
2025-01-25
Senior R&D Engineer - RISC-V Matrix Extensions (Italy/Europe based)
2025-01-25
Senior R&D Engineer - RISC-V Memory Hierarchy (Italy/Europe based)
2025-01-25
Senior R&D Engineer - RISC-V Matrix Extensions (Italy/Europe based)
2025-01-25
Senior R&D Engineer - RISC-V Memory Hierarchy (Italy/Europe based)
2025-01-25
Principal DFT Engineer
2025-01-22
Principal DFT Engineer
2025-01-22
Principal DFT Engineer
2025-01-22
Principal DFT Engineer
2025-01-22
Staff/Principal DFT Engineer
2025-01-22
Senior DFT Engineer (Italy based)
2025-01-21
Senior DFT Engineer (Italy based)
2025-01-21