Design Verification Engineer - System Verilog/UVM (Semiconductor / Automotive)

Senior Digital Verification Engineer

A fantastic opportunity for an experienced Digital Verification Engineer to join a leading Global Semiconductor Company at their site in Nijmegen, The Netherlands.

In this role you will have the opportunity to contribute to next generation In-Vehicle Networking products for the ongoing evolution of self driving cars.

Your Responsibilities

• Digital Verification Engineer (UVM) for Product/IP development; specify, execute and report Verification simulations to proof the functional, structural and performance compliance before IC Mask Ordering.
• Define and apply verification testbenches, test-cases, debug simulations, provide coverage reporting.
• Collaborate with other teams part of Product development (i.e. system, architecture, industrial engineering, application)

Your Profile

• Bachelor or Master's Degree in electronics or information engineering,
• 4+ years’ experience in IC verification
• Broad experience and knowledge of verification methodologies and tooling, including SystemVerilog, UVM, constraint random verification and assertions.
• Hands-on experience with RTL design languages (VHDL/Verilog), scripting languages like Python, TCL and Perl, V-diagram, tools for requirements management (DOORS/ELM7)

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