Senior Staff Verification Engineer

Senior Staff Verification Engineer – Semiconductor Industry

Location: Dublin or Cork, Ireland (Hybrid – 2 days per week onsite)

A global leader in the semiconductor industry is seeking an experienced Senior Staff Verification Engineer to join its team in Ireland. This role offers the opportunity to contribute to cutting-edge IP, subsystem, and SoC development projects, working within a collaborative and innovative engineering environment.

Key Responsibilities:

• Contribute to the design and definition of scalable verification infrastructure, including testbench components and reusable test cases.
• Define and execute verification strategies (constraint random, directed, formal, etc.) for digital and mixed-signal IPs and subsystems.
• Develop, maintain, and enhance UVM/OVM/SystemVerilog-based verification environments.
• Create, document, and execute comprehensive test plans; develop, debug, and refine random constraint verification suites.
• Collaborate with design and post-silicon validation teams to ensure robust and timely product delivery.
• Drive improvements in verification methodologies to enhance efficiency and coverage.

Essential Requirements:

• Master’s degree in Electrical Engineering with 5–7 years of relevant experience, or Bachelor’s degree with 7–9 years.
• Strong knowledge of verification methodologies such as UVM, OVM, and SystemVerilog.
• Proven track record of developing verification infrastructure for complex digital/mixed-signal IPs, subsystems, or SoCs.
• Hands-on experience with SystemVerilog Assertions, scoreboards, functional and code coverage metrics.
• Understanding of power-aware verification (UPF) and gate-level simulation.
• Proficiency in scripting languages (Python, C, Tcl, Perl, etc.) for test automation.
• Strong problem-solving ability, initiative, and communication skills, with the ability to work effectively in cross-functional teams.

Interested to know more?

Apply here with your CV .

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