Digital Design Engineer - ASIC / Verilog / C/C++

We are working with an industry-leading company at the forefront of 5G innovation, transforming connectivity and shaping the future.

They are looking for an EVA/Video Design Engineer to join their Multimedia Video and Computer Vision HW Design team to develop cutting-edge IP Cores for video CODEC standards and advanced computer vision applications.

Key Responsibilities:

• Implement advanced computer vision algorithms (e.g., feature detection, object detection, machine learning, depth perception) for applications like cameras, AR/VR, and automotive.
• Collaborate with hardware, systems, and firmware teams to define specifications and develop IP Cores.
• Design micro-architecture and RTL (Verilog/SystemVerilog) optimized for performance, area, and power.
• Support design verification (DV) teams in test planning, functional verification, and coverage closure.
• Debug issues in simulation/emulation, identify root causes, and implement fixes.
• Analyze linting, synthesis, CLP, power, CDC, and LEC reports to ensure design quality.
• Assist with post-silicon debug and maintain thorough design documentation.
• Communicate effectively across teams and manage tasks efficiently.

Key Qualifications:

• Experience in ASIC/Logic design, verification, or related fields.
• Proficiency in Verilog, SystemVerilog, C/C++, and Python/Perl.
• Expertise in micro-architecture, RTL design, synthesis, and optimizations.
• Familiarity with low-power, high-performance design and video/image processing.
• Knowledge of video standards (H.264, HEVC, AV1, VVC) and computer vision/machine learning.
• Experience in design verification and post-silicon debugging.
• Leadership experience in designing IP blocks is a plus.
• Ability to work in a global, multidisciplinary team developing high-volume applications.

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